Recent developments in integrated circuit technology have shown remarkable promise for reducing logic and memory circuits to nanoscale or molecular-scale. One architecture for nanoscale integrated circuits provides a “mosaic” or an electronically interconnected collection of small irreducible silicon or “moletronic tiles”. Although the individual tiles are extremely compact, nanoscale circuits suffer from many of the same limitations of current microscale silicon circuits. In particular, the number of electronic interconnections between circuit units (e.g., between chips or internal circuit units) increases as the level of integration increases (i.e., as the feature size decreases). For example, according to Rent's Rule, the number Np of pins or external connections to a logic circuit is generally proportional to a power γ of the number Ng of gates in the logic circuit as indicated in Equation (1). In Equation (1), the proportionality constant κ and the power γ depend on architecture and implementation of the logic circuit. For most microprocessor architectures, for example, proportionality constant κ in Equation (1) is typically between 1 and 2, and power γ is between 0.5 and 0.6.Np=κNgγ  (1)
FIG. 1 illustrates a typical architecture 100 for connection of a CPU 110 to random access memory (RAM) 130. In architecture 100, CPU 110 use/generates logical addresses that ultimately must be converted into a physical memory address identifying specific data locations in RAM 130. A multiplexer 120 must be designed to map the logical addresses from CPU 110 to physical addresses identifying the physical location of the bytes of RAM 130 being accessed. Ultimately, electrical wires in RAM 130 and between RAM 130 and multiplexer 120 must connect CPU 110 to every byte of RAM 120. In principle, stages of sub-multiplexers can be designed (each of which communicates with one multiplexer above and many below), but the buffering and switching that must be incorporated into any such architecture increases circuit complexity and limits the performance of the architecture 100 through increased resistance and capacitive delays.
Problems with architecture 100 get worse as components 110 and 130 shrink from micrometer to nanometer dimensions. In particular, as the gate counts increase, the number of interconnects required increases as indicated be Rent's Rule, i.e., Equation 1, and the interconnects require relatively more area. The size of external interconnects generally cannot be decreased below a minimum size required to make electrical connects to other devices or printing circuit, thus the size limitations of external interconnects fail to full advantage of the miniaturization advantages of moletronic devices. Further, the intrinsic capacitance of the multiplexing electronics having closely spaced lines for interconnections can greatly exceed that of moletronic circuit tiles within CPU 110 or RAM 130, and the interconnect impedance becomes a limiting factor to signal speed. Accordingly, an efficient architecture that provides fast interconnections of circuit units in a small circuit area is desired.